NePSim: A Network Processor Simulator with Power Evaluation Framework


There is an increasing interest in the network processor (NP) architecture design as well as its power dissipation characteristics. However, there has not been an open-source simulation infrastructure that makes the performance/power tradeoffs in NPs clearly visible to computer architects.

NePSim is the first open source integrated infrastructure for analyzing and optimizing NP design and power dissipation at architecture-level. NePSim contains a cycle-accurate simulator for a typical NP architecture (Intel's IXP1200), an automatic verification framework for testing and validation, and a power estimation model for measuring the power consumption of the simulated NP. NePSim achieves satisfactory accuracy in both performance and power modeling.

Following the success of NePSim, NePSim2 is developed to model more advanced network processor architectures such as Intel IXP2xxx NPs. There are significant differences between IXP2xxx and IXP1200, to name a few, more microengines and threads, MEv2 instruction set, new interconnection (MSF), next neighbor registers,and generalized signaling scheme, etc. These new features make the development of NePSim2 very challenging. We have incorporated a set of cryptographic benchmark applications along with a number of basic testcases. Our goal is to make NePSim2 a complete performance and power simulation tool for modern NPs like IXP2xxx processors. We are in active development and welcome contributions from the community.

NePSim is proudly highlighted in Intel IXA Summit and Intel IXA Newsletter 2004.

The Simulator

The NePSim2 beta release is available for non-commercial use only.
Download NePSim2

The NePSim 1.0 is available for non-commercial use only. This release does not include SRAM or SDRAM power model.
Download NePSim 1.0

The verification tool (LOCGEN) can be downloaded from PAC.


Jia Yu, Jun Yang, Shaojie Chen, Yan Luo and Laxmi Bhuyan, "Enhancing Network Processor Simulation Speed With Statistical Input Sampling," 2005 International Conference on High Performance Embedded Architectures & Compilers, LNCS Vol. 3793, pp. 68 - 83, 2005, Springer-Verlag Publishers.

Yan Luo, Jia Yu, Jun Yang, Laxmi Bhuyan, "Low Power Network Processor Design Using Clock Gating", IEEE/ACM Design Automation Conference (DAC), Ahaheim, California, June 13-17, 2005.

Yan Luo, Jun Yang, Laxmi Bhuyan, Li Zhao, "NePSim: A Network Processor Simulator with Power Evaluation Framework", IEEE Micro Special Issue on Network Processors for Future High-End Systems and Applications, Sept/Oct 2004.

Xi Chen, Yan Luo, Harry Hsieh, Laxmi Bhuyan, F. Balarin, "Utilizing Formal Assertions for System Design of Network Processors," Design Forum, Design Automation and Test in Europe (DATE), 2004.


Yan Luo, Jun Yang, Laxmi Bhuyan, Li Zhao, "NePSim: A Network Processor Simulator with Power Evaluation Framework" , Intel IXA Education Summit 2004, September 22-23, Massachusetts.

Additional Information

Please send emails to yluo at to report bugs, ask questions or get more information. We have also set up a mailing list for discussions.
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Thanks for using NePSim.
Last update @ 04-23-2006 by Yan Luo (yluo at cs ucr edu)